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Memory hierarchy
Results: 173

#	Item
101	Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization ´ Garzar´an, Lawrence Rauchwergery , and Josep Torrellas Milos Prvulovic, Mar´ıa Jesus University of Illinois at Urbana-Champaign Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-03-23 12:50:54 Computer memory Cache coherency Central processing unit CPU cache Cache Multi-core processor Speedup Automatic parallelization Memory hierarchy Computing Parallel computing Computer architecture
102	USING AN ADAPTIVE HPC RUNTIME SYSTEM TO RECONFIGURE THE CACHE HIERARCHY SC’14, Nov. 20, 2014 Ehsan Totoni, Josep Torrellas, Laxmikant V. Kale Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-12-19 19:14:48 Central processing unit Ø Slashed zero Numbers Information Computer memory Cache CPU cache
103	SWICH: A PROTOTYPE FOR EFFICIENT CACHE-LEVEL CHECKPOINTING AND ROLLBACK EXISTING CACHE-LEVEL CHECKPOINTING SCHEMES DO NOT CONTINUOUSLY SUPPORT A LARGE ROLLBACK WINDOW. IMMEDIATELY AFTER A CHECKPOINT, THE NUMBER OF INSTRU Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-05-03 11:36:50 Computer memory Computer engineering Cache Application checkpointing CPU cache Microarchitecture SPARC64 Memory hierarchy Runahead Computer hardware Computer architecture Central processing unit
104	Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy Ehsan Totoni, Josep Torrellas, Laxmikant V. Kale Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA E Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-08-13 13:31:19 Computer memory Computer hardware CPU cache Central processing unit Instruction set architectures Cache algorithms Memory hierarchy Blue Gene Xeon Computer architecture Computing Cache
105	CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses LUIS CEZE, KARIN STRAUSS, JAMES TUCK, and JOSEP TORRELLAS University of Illinois at Urbana–Champaign and JOSE RENAU Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 00:10:17 Central processing unit Computer memory Runahead Cache CPU cache Branch predictor Microarchitecture Memory hierarchy Speculative execution Computer architecture Computer hardware Computer engineering
106	Microsoft Word - HP _XP24000_SPC2-FDR.doc Add to Reading List Source URL: www.storageperformance.org Language: English Data management Computing Data Extensible Storage Engine Memory hierarchy Database
107	Microsoft Word - HP_StorageWorks-8000-EVA_SPC2-FDR_2005_11_22.doc Add to Reading List Source URL: www.storageperformance.org Language: English - Date: 2010-03-12 04:30:40 Extensible Storage Engine Memory hierarchy Computing
108	The Impact of Paravirtualized Memory Hierarchy on Linear Algebra Computational Kernels and Software Lamia Youseff Keith Seymour Add to Reading List Source URL: icl.cs.utk.edu Language: English - Date: 2008-04-22 16:19:11 Numerical software Xen General Matrix Multiply Paravirtualization Kernel Virtual machine Mach Basic Linear Algebra Subprograms Hyper-V System software Software Numerical linear algebra
109	SPC Benchmark 2™ Full Disclosure Report Add to Reading List Source URL: www.storageperformance.org Language: English - Date: 2012-07-27 15:44:54 Data management Computing Data Extensible Storage Engine Database Memory hierarchy
110	SPC Benchmark 2™ Full Disclosure Report Add to Reading List Source URL: www.storageperformance.org Language: English - Date: 2012-04-13 04:31:14 Computer data storage Data management Computing Data Extensible Storage Engine Memory hierarchy Database

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